1. Field of the Invention
The present invention relates to a data write circuit connected to a nonvolatile memory cell transistor array which can prevent the possibility of data being erroneously written into a memory cell.
2. Description of the Related Art
Data write circuit 20, as shown in FIG. 1, is conventionally used for a nonvolatile memory, such as an EPROM. In such a memory, a plurality of floating gate type memory cell transistors MC have their drains connected to bit lines BL for memory cell array MA. Data write circuit 20 and data readout circuit 21 are connected to bit lines BL through bit line select transistor T.sub.BL. Data write circuit 20 has one MOS transistor 22, such as an N-channel transistor, connected across a write voltage terminal V.sub.pp and bit line BL via a bit line select transistor T.sub.BL. Write signal line WE is connected to the gate of transistor 22.
The operation of the nonvolatile memory cell transistor array is as follows.
Let it be assumed that a write operation is performed at a time of data "0". When a high voltage V.sub.pp is applied to write signal line WE at a write time, write transistor 22 is turned ON. With transistor 22 in an "ON" state, a voltage on the bit line BL for a specific column connected to the bit line select transistor selected by the output of the column decoder becomes level V.sub.pp. At this time, voltage V.sub.pp is applied to the word line WL on a specific column selected by the output of the row decoder, and hence the voltage V.sub.pp is applied to the same column which is connected to the word line WL on the control gates of memory cell transistors MC. As a result, voltage V.sub.pp is applied across the drain D and control gate CG of a selected specific memory cell transistor MC as shown in FIG. 2, thereby causing a large current to flow across the drain and the source S (grounded) of the same transistor. Hot electrons are drawn across the channel section and into a floating gate FG by voltage V.sub.pp applied to the control gate CG. As a result, data "1" is written into the selected memory cell.
After the "1" data is written into the select memory cell, voltage V.sub.pp is no longer applied to the write signal line WE, and write transistor 22 is placed in a non-action (OFF) state.
With write transistor 22 OFF, noise is adversely produced due to some effect on that V.sub.pp voltage system. If the noise level exceeds level V.sub.pp, a "punch-through" occurs in transistor 22 due to the application of a high voltage in excess of a withstand voltage to that transistor. As a result, high voltage will be erroneously applied to each bit line which is connected as a load of write transistor 22. Even if voltage V.sub.pp is applied to a selected column in memory array MA of a memory cell array matrix in the memory cell transistors whose gates are connected to the "not selected" column may produce hot electrons into their floating gates when a high voltage on the bit line is applied to the drains of the memory cell transistors. Such an event, when occurring infrequently (for example, once), produces no risk of data inversion. However, if such an event occurs several times repetitively, then data inversion may occur in the form of a "write error."
In the aforementioned EPROM, when the memory cell transistor is used, for example, as some type of a flag, a "write error" resulting from the noise of the V.sub.pp voltage prominently occurs due in part to a small transistor load, in particular of write transistor 22.